The present invention relates to a nonvolatile memory device and method for fabricating the same, and more particularly to a nonvolatile memory device (and method for fabricating the same) having an increased coupling ratio of a floating gate and control gate, and thereby an improved programming characteristic of the memory device.
As shown in FIG. 1, a conventional flash memory cell is formed in a manner that an active region (A) is defined between field insulating layers 21, a control gate electrode line 25 is formed perpendicular to the field insulating layer 21, and a floating gate 23 is formed on a portion where the active region (A) and the control gate meet. The floating gate 23 is isolated from the active region and the control gate.
A method for fabricating the conventional flash memory cell will be explained below. Field insulating layer 21 is formed on a substrate 20, and a gate oxide layer 22 is formed on the substrate. Polysilicon is deposited on the exposed surfaces, and patterned in a first direction to form floating gate 23. An interlevel insulating layer 24 is formed on the exposed surfaces, and polysilicon is deposited thereon and patterned in a second direction, perpendicular to the first direction, to form control gate 25. Here, floating gate 23 is formed by etching the first-direction-patterned polysilicon layer using control gate 25 as a self-aligning mask, to form a final floating gate 23. Then, ions are implanted into an exposed portion of the substrate, to form a source and drain on both sides of the gate. The above-mentioned flash memory cell is programmed by injecting electrons into floating gate 23, or not, to change the threshold voltage of its channel.
The programming of the memory cell is performed by applying a voltage to the control gate and drain electrode (not shown). This voltage is relatively higher than that applied to the source electrode (not shown). Here, the voltage applied to the control gate is induced to the floating gate according to the coupling effect, and the induced voltage draws hot electrons generated nearby the drain. The coupling induced voltage induced to the floating gate is proportional to the contact area of the control gate and floating gate. That is, the higher a coupling ratio kc is, the larger the induced voltage is. If coupling ratio kc is large, the programming efficiency and characteristic are improved. Coupling ratio kc is determined by a capacitance Cpp between the control gate and floating gate, and a capacitance Cox between the floating gate and silicon substrate. Coupling ratio kc of a stacked gate flash memory cell is Cpp/(Cpp+Cox). Accordingly, the coupling ratio kc becomes higher as capacitance Cpp becomes larger than capacitance Cox. For the purpose of increasing capacitance Cpp, the interlevel insulating layer's dielectric constant must be made larger, or its thickness thinner. Otherwise, the superposed area of the floating gate and control gate must be increased.
However, a conventional method for increasing the superposed area of the floating gate and the control gate causes an increase of the memory cell area. In order to make the superposed area of the floating gate and control gate relatively larger than the superposed area of the floating gate and silicon substrate, the floating gate should cover a larger portion of the field insulating layer 21, as shown in FIG. 1. This increases the width of the floating gate. As a result, the memory cell size is increased.
To apply a voltage which is easily programmed to the floating gate without enlarging the area of a portion of the floating gate, which portion is formed on the field insulating layer, the voltage applied to the control gate should be increased. The greater the voltage applied to the floating gate, the shorter the time required for electron injection into the floating gate to reach saturation. This increases the programming speed of the memory cell.